fault test generation
英 [fɔːlt test ˌdʒenəˈreɪʃn]
美 [fɔːlt test ˌdʒenəˈreɪʃn]
网络 故障测试产生; 故障测试生成
双语例句
- Based on cell fault model, the paper studies test pattern generation and self test of tree adder, which is frequently used in the high performance processors.
时延故障对高速运算电路性能有着关键性的影响，本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。 - Therefore, we combine Petri net analysis method with software simulated circuit, put forward Petri net based simulated circuit model, Petri net based fault model and related test set generation method, test set simplification method.
因此，将Petri网的分析方法与计算机仿真的数字电路相结合，提出了基于Petri网的仿真电路模型、故障模型以及相关的测试生成、测试集化简方法。 - The Multiple Fault Form Coexistence Test Generation Algorithm with Both W-O and W-A Diagonal Independence
同时具备W-O和W-A对角独立性的多故障测试生成算法 - Distinguishable Fault Methods of Circuits Test Generation
电路测试的可区分故障算法研究 - Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文对VLSI测试中的两个主要问题&故障模拟和测试产生进行了深入的分析和研究。 - A functional fault model and a test generation procedure for digital systems
数字系统功能级故障模型及测试产生方法 - Base on the existing synchronous sequential circuits fault simulator-HOPE, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly.
本文在同步时序电路故障模拟器&HOPE的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。 - This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
详细分析了固定故障所反映出的状态变换特征，提出状态变换故障模型以及相对应的测试生成压缩方法； - Based on the method of critical path tracing, a set of effective strategies and accelerated techniques, and two algorithms, one for fault simulation and another for test generation, are proposed.
以临界路径跟踪法为基础，提出了一系列有效的策略和加速技术，以及以此为基础的故障模拟算法和测试产生算法。 - The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66%), but the fault coverage and time performance are lower than gate-level test generation.
实验数据表明分层测试产生算法能大大压缩电路测试集（约为66%），而故障覆盖率有略微下降，时间性能也有些许降低。 - The experimental results for benchmark circuits show that the proposed algorithm can achieve higher fault coverages and more compact test sets when compared to other similar test generation algorithms.
针对国际标准时序电路的验证结果表明，与同类算法相比，该算法可以获得较高的故障覆盖率和较小的测试矢量集。 - Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。 - This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。 - Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm.
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。 - First, the thesis analyzes the delay fault testability of ETG PLA, which is a kind of two-level circuit with test generation complexity being linear to the number of products.
首先从特殊的两级电路，ETGPLA，着手进行可测试性分析。ETGPLA是一种逻辑功能测试向量产生复杂度与乘积线数成正比的两级电路。 - Because the probability of happening multi-fault for system is big during debug phase and the possibility of happening single fault is bigger during usage phase, the test generation problem for single stuck-at fault is the hot spot of research in the world.
又因为系统在调试阶段发生多故障的概率较大，但在使用阶段发生单固定型故障的可能性要大得多，因此，单固定型故障的测试生成问题一直是国际上研究的热点。 - Fault Collapsing and Test Generation for At-speed Current Testing
全速电流测试的故障精简和测试生成 - Research on RTL Fault Models and Test Generation
集成电路寄存器传输级故障模型与测试生成研究 - This method can enhance the efficiency of software modeling, free testing staff from heavy test case coding, shorten the test case length with the same fault coverage as manual test case generation.
该方法使测试人员从繁重的测试例编写工作中解放出来，在相同差错覆盖的条件下可以有效的缩短测试例的长度，提高软件测试开发的效率。 - Generational ideas and fault diagnostic capabilities in terms of the classical boundary-scan test vector generation algorithm is a careful analysis and summary; Based on testing of completeness and the requirements, algorithm presents a right to the value of such optimized inter-Even testing algorithm.
在生成思想和故障诊断能力等方面，对经典的边界扫描测试矢量生成算法进行了认真地研究和总结。根据测试算法完备性和紧凑性的要求，提出了一种经过优化的等权值互连测试算法。 - The paper describes The work theory, failure mode and fault mode of memory are described. Secondly, study the test methods and algorithm of test generation of memory is studied. The algorithms are described according to the relations between test pattern graphics 'length.
论述了存储器的工作原理、故障模式以及故障模型，然后研究了存储器的测试方法，产生测试图形的测试算法，并按照图形的长度进行了分类研究。